Description

The 74HC107D is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Note: for more technical details go through Datasheet in the attachment section 

Features & Specifications:

1. Wide supply voltage range from 2.0 V to 6.0 V
2. CMOS low power dissipation
3. High noise immunity
4. Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
5. Complies with JEDEC standards:
   • JESD8C (2.7 V to 3.6 V)
   • JESD7A (2.0 V to 6.0 V)
6. Input levels:
   • The 74HC107: CMOS levels
   • The 74HCT107: TTL levels
7. ESD protection:
   • HBM JESD22-A114F exceeds 2000 V
   • MM JESD22-A115-A exceeds 200 V
8. Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Package Includes:

1 x 74HC107D