Description

The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier internet connection for embedded systems using SPI (Serial Peripheral Interface).

W5500 suits users in need of stable internet connectivity best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY. Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE, …, which has been proven through various applications over many years. W5500 uses a 32Kbytes internal buffer as its data communication memory.

Note: for more technical details go through Datasheet in the attachment section 

Features:

1. Supports following Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
2. Supports 8 independent sockets simultaneously
3. Supports Power down mode
4. Supports Wake on LAN over UDP
5. Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
6. Internal 32Kbytes Memory for Tx/Rx Buffers
7. 10BaseT/100BaseTX Ethernet PHY embedded
8. Support Auto Negotiation (Full and half duplex, 10 and 100-based)
9. Not support IP Fragmentation
10. 3.3V operation with 5V I/O signal tolerance
11. LED outputs (Full/Half duplex, Link, Speed, Active)

Specifications:

1. Operating Voltage: 3.3V operation with 5V I/O signal tolerance
2. Memory: Internal 32Kbytes Memory for Tx/Rx Buffers
3. IP Fragmentation: No
4. LED outputs: (Full/Half duplex, Link, Speed, Active)

Package Includes:

1 x WIZnet W5500